The present invention relates to an integrated circuit arrangement comprising
a semiconductor layer which is doped with ions of desired polarity, PA1 mutually spaced component regions in the semiconductor layer surface, of which at least two regions are doped with ions of opposite polarity to the semiconductor layer, PA1 a first insulating semiconductor oxide layer on the semiconductor layer having cut-outs for electric connection to the semiconductor layer, and PA1 layers of polycrystalline semiconductor material on the semiconductor oxide layer, wherein the integrated circuit is intended for connection to a voltage which is greater than a field threshold voltage so as to cause charge inversion to occur in the semiconductor layer. The invention also relates to a method for producing the arrangement.
The risk that so-called parasite components will occur in integrated semiconductor circuits is often present. An example of a so-called parasite component is the parasite-MOS transistor (Metal Oxide Semiconductor) which occurs between the base regions of two bipolar transistors. The integrated circuit is built on a semiconductor substrate and includes an epitaxial layer in which the base regions are diffused. The base regions are spaced so wide apart as to normally prevent the two bipolar transistors from disturbing one another. Several other layers are found on the epitaxial layer, for instance an insulating first oxide layer which lies immediately on the epitaxial layer, electrical connections and an electrically insulating protective layer which forms the uppermost layer of the composite structure. This protective layer may become covered with an undesirable film of moisture, which is electrically conductive and connected, for instance, to a terminal voltage of the integrated circuit. The moisture film functions as a gate and lies on the potential of the terminal voltage and attracts charges in the epitaxial layer between the base regions, so-called inversion, therewith creating the aforesaid parasite-MOS transistor. In order for inversion to take place, it is necessary for the potential of the moisture film to exceed a field threshold voltage. The problem of parasite-MOS transistors can be avoided relatively easily in the case of integrated circuits which are intended for low voltages, for instance memory circuits in computers with terminal voltages about 5 volts. In such integrated circuits, inversion can be counteracted in a known manner, by raising the field threshold voltage with the aid of an additional diffusion or implantation.
In the case of circuits which are intended for high supply voltages, this method requires wide spacing between the diffusion which raises the threshold voltage and, for instance, a base diffusion, in order not to degrade the breakdown voltage of the transistor. Another known alternative involves the use of a metal screen. The metal screen is connected to the potential of the epitaxial layer and prevents parasitic inversion from taking place beneath the screen. The drawback with this method lies in the difficulty experienced in running the metal conductors and connecting these conductors to peripheral components. The conductor layout and the screens are effected with one and the same metal layer and it is difficult to avoid short circuiting. One known solution involves the use of two metal layers, one for the screens and one for the conductor lay-out. This solution, however, renders the manufacturing process much more complicated and much more expensive, because it is necessary to introduce an additional process and masking step. The oxide layer which needs to be deposited on the first metal layer as an electrical insulation against the second metal layer constitutes a particular problem. The metallization cannot withstand high temperatures and it is necessary for the oxide layer to cover the topography of the disk uniformly in order to enable a good second metallization to be achieved. The lower the highest temperature available, the more difficult this is to achieve.
Other layers additional to the metal screen are often applied to the first oxide layer. One example of this is a polycrystalline layer around the base of a transistor, this layer forming a screen which prevents an electrical breakdown at the base edges. The polycrystalline layer and the metal screen are applied in separate process steps with the aid of separate masks and these process steps are relatively expensive. One such polycrystalline base screen is found described in more detail in Revue De Physique Appliquee, Tome 13, Decembre 1978, M. Roche: "An Advanced Processing Technology for High Voltage Bipolar IC's". In this case, the screen is connected through a metallic connection to a potential which is positive in relation to the potential of the epitaxial layer. Another example of a polycrystalline layer is found described in IEEE Transactions on Electron Devices, Vol. 36, No. 9, September 1989, Denny Duan-Lee Tang et al: "The Design and Electrical Characteristics of High-Performance Single-Poly Ion Implanted Bipolar Transistors". In this article, the polycrystalline layer referred to forms an emitter contact for a transistor.